1. Field of the Invention
This invention relates to electronic systems, and more particularly, to memory devices in electronic systems.
2. Description of the Related Art
Computer systems employ different types of memory for various functions. These types of memory include dynamic random access memory (DRAM), static random access memory (SRAM), and various types of read-only memory (ROM), among others. Many of these types of memories may be implemented using field-effect transistors (FETs), and thus may be subject to certain problems associated therewith.
One problem that may affect FET-based memory circuits is leakage. Leakage can be defined as a zero-signal current flowing across a reverse-biased semiconductor junction. In the case of a FET, this means that some current may be flowing through the drain-source junction even if the transistor is turned off (e.g., when VGS<Vt for an N-channel FET). Leakage currents are undesirable in a memory circuit, as they may cause a loss of information and/or erroneous operation.
Another problem that may affect FET-based memory circuits are bi-polar currents. Bi-polar currents may occur in a FET when the FET operates in the triode region (e.g., VDS<=VGS−Vt in a N-channel FET). Bi-polar currents in a FET-based memory are typically transient currents. However, as with leakage currents, bi-polar currents in a FET-based memory circuit may cause a loss of data or erroneous operation.
Bi-polar and leakage currents may be somewhat reduced by using transistors having larger feature sizes. However, such transistors may have slow switching speeds compared to their smaller counterparts, and thus may be unsuitable for the demands of higher-speed computing systems. Thus, other methods of reducing bi-polar and leakage currents must be found.
FIG. 1 is a schematic diagram of one embodiment of a read-only memory (ROM) structure that illustrates problems associated with leakage and bi-polar currents. More particularly, FIG. 1 illustrates a one-hot multiplexer structure for a plurality of local bitlines that are coupled to a global bitline. Each local bitline is coupled to a ROM cell, which, if programmed to a logic ‘1’ (or logic high level), has a connection broken either on the gate or the drain of the NMOS transistor shown in this example. If no connection is broken, the ROM cell is thus programmed to a logic ‘0’ (or logic low level). If a ROM cell is programmed to a logic high level in this circuit structure, its associated local bitline will tend to float, and will rely on the weak keeper circuit coupled to node A to hold it at a logic high value. As implied by its designation, the keeper circuit is weak in order to enable faster switching speeds.
When one of the passgates in the one-hot multiplexer is turned on, the value present on the local bitline is allowed to propagate through to the inverter and eventually, to the global bitline. While the one passgate is turned on, the remainder of the passgates remain turned off. Thus, the weak keeper circuit must also hold a logic high value on any bitlines associated with a programmed ROM cell since those bitlines are floating, and must also hold a logic high on the selected bitline if its associated cell is programmed. However, due to leakage and bi-polar currents, the keeper circuit (since it is weak), may be unable to hold a logic one on each of the bitlines, including the selected bitline. Thus, the voltage at node A may fall below a value that is recognized by the inverter as a logic ‘1’. If this happens, the output of the inverter may become a logic high value and thus turn off the two PMOS transistors used in the weak keeper circuit, while also turning on the NMOS transistor coupled to the global bitline. Thus, in this scenario, an incorrect data value may be propagated to the global bitline. While this problem may be mitigated by using a strong keeper circuit, its use may be at the expense of operating speed.